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 environments. To handle the changes of graph structures after the IoT devices have been deployed in edge environments%2C in this paper we propose to combine an online sequential training algorithm with node2vec. The proposed sequentially-trainable model is implemented on an FPGA (Field-Programmable Gate Array) device to demonstrate the benefits of our approach. The proposed FPGA implementation achieves up to 205.25 times speedup compared to the original model on ARM Cortex-A53 CPU. Evaluation results using dynamic graphs show that although the accuracy is decreased in the original model%2C the proposed sequential model can obtain better graph embedding that achieves a higher accuracy even when the graph structure is changed.?quality=80&w=800)
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- FPGA-based graph processing accelerator framework. | Download Scientific Diagram
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- Figure 1 from An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm ...
- Figure 1 from An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm ...
- Figure 1 from An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm ...
- Table 1 from An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm ...
- Table 2 from An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm ...