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(PDF) A CMOS gate array architecture for digital signal processing applications

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Figure 10 from A subnanosecond 8K-gate CMOS/SOS gate array | Semantic Scholar

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Figure 1 from A CMOS gate array with dynamic-termination GTL I/O circuits | Semantic Scholar

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Figure 3 from A CMOS gate array with dynamic-termination GTL I/O circuits | Semantic Scholar

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